Adjunct Professors


JOHN A. VLONTZOS 

Full Professor AIT

 



EXPERIENCE

  • INTRACOM S. A. Paiania, Attica 
    2002-present Deputy General Manager for R&D, Technical Division. Managing R&D activities within Intracom with emphasis on Software R&D, digital TV and Internet Systems.. Managing research and development activities in Interactive Television, Internet over Satellite applications and embedded systems. 
    1999-present Head, New Technologies Department. Managing research and development activities in Interactive Television, Internet over Satellite applications and embedded systems.
    1996-1999. Chief architect of Intracom’s Internet over Satellite product. The product has been licensed among others by the Japanese Ministry of Education (1300 schools), Reuters, Globecast, Gilat, News Corp, Loral/Cyberstar. 
    1993-1996 Group Leader, VLSI research. Developed VLSI systems for MRF based image processing and managed research and development for EU funded projects in the VLSI area. 
    1992-1993. Research in image compression, medical image processing, architectures for special purpose VLSI processors. Coordination of image processing research programs. 
  • National University of Athens, Athens Greece, 1997-1998. Adjunct Professor teaching a course on special purpose DSP processors including systolic and array processors. 
  • SIEMENS Corporate Research Inc. Princeton, N. J. 1989-1992 Research Scientist: Neural Systems design. Development of neural algorithms for stereo vision, motion estimation and sound location using artificial cochlea and retina models. (1989-1990) Systolic Array Processor Design, architectures, tools and methodologies. Design and construction of a systolic linear algebra processor, a morphological filtering processor for medical imaging applications and graphical tools for systolic array design. 
  • Princeton University Princeton, N. J.1990-1992 Adjunct Professor: Teaching a Switching Theory and Finite Automata Course 
  • Princeton University Princeton, N. J. 1988-1989 Member of Research Staff: Design of a VLSI array processor for Neural Network Simulation and Adaptive Signal Processing algorithm implementation. 
  • University of Southern California Los Angeles, CA. 1985-1988 Instructor and Research Assistant: Taught Lisp Courses and performed research in computer architectures for Image Processing.  
  • National Defense Research Center Athens, Greece 1983–1985 Research Consultant: Research and development of Linear Prediction Vocoder and encryption system. 
  • National Technical University Athens, Greece 1983-1985 Instructor: Taught Programming and Parallel Computer Architecture courses.

EDUCATION

  • University of Southern California Los Angeles, CA. 1985-1989 
    Ph. D. in Computer Engineering. 
    Thesis:“Hidden Markov Models for Character Recognition” 
    Specialization: Array Processor Design for Pattern Recognition and Computer Vision. 
  • University of Rhode Island Kingston, R. I 1981-1983 
    M. Sc. in Electrical Engineering. 
    Thesis: “Correlation Techniques for Zooplankton Classification” 
    Specialization: Pattern Recognition. 
  • National Technical University Athens, Greece 1974-1979 
    B. Sc in Electrical Engineering. 
    Thesis: “TDM-FDM Transmultiplexer with Reduced Computational Complexity”
    Specialization: Digital Signal Processing. 

RESEARCH RELATED ACTIVITIES

  • Design of a wavefront array processor for image processing.(1987) 
  • Compilers for dataflow and wavefront processors (1987) 
  • Neural Networks and self organizing systems.(1988-1989) 
  • Parallel Processors for AI applications.(1988-1990) 
  • Hidden Markov Models for Character Recognition.(1988-1990) 
  • Stereo Vision and Motion Estimation algorithms based on artificial neural network sensors.(1989-1990) 
  • Design of a systolic Linear Algebra processor (1990-1993) 
  • Design of a Morphological filter processor(1990-1994) 
  • Design of tools for the automatic generation of systolic architectures from algorithmic descriptions(1990-1993) 
  • Design and implementation of IP over satellite protocols (1994-1996) 
  • Design and implementation of reliable IP multicasting protocols (1996-1998)
  • Design and implementation of multiscreen presentation systems based on satellite transmission. (1998-1999)
  • Design and implementation of synchronized multimedia languages (1998-present) 

COMPUTER EXPERIENCE

1. Hardware Designed 
  • Pattern Recognition system based on an array of microprocessors (used by the National Oceanic and Atmospheric Administration) (1983). 
  • TI TMS320 based signal processing systems (Used by the Greek Armed Forces) (1985). 
  • NEC µ. PD7281 Dataflow chip based array for image processing (1987).
  • Custom VLSI array processor for Neural Network Simulation and Adaptive Signal Processing (1989).(Princeton Special Purpose Supercomputer) 
  • Systolic Array for Linear Algebra (1990-1992) Siemens Corp. Research
  • Morphological systolic array processor for medical imaging (1990-1992) 

2. Software Developed:

  • Internet over Satellite software system 1996-1999
  • Graphics based tools for automatic generation of systolic architectures from algorithmic specification (1990-1993) 
  • Graphics based environment based on UNM Khoros system for signal and image processing (1990-1992) 
  • Systolic algorithm library of microprograms for the linear algebra machine. (1990-1994) 
  • Hierarchical system using hidden Markov models for character recognition (1988). 
  • Transputer based parallel systems for pattern recognition (1988) 
  • FP compiler for algorithm parallelization (1987).
  • FORTH compiler for TMS320 system (1985). 
  • MC68000 Assembler (1985). 
  • FIR filter design program (1978). 
  • Operating Systems: UNIX, Linux,VMS, HP RTE3-5, CDC NOS, MSDOS. 
  • Languages: Java,Fortran, Lisp, Prolog, Pascal, C, Basic, Occam, FP, SISAL.

OTHER PROFESSIONAL ACTIVITIES

  • Chairman, Fourth IEEE-SP Workshop on Neural Networks for Signal and Image Processing 
  • Organizing Committee, First IEEE-SP Workshop on Neural Networks for Signal and Image Processing (Sep. 1991) 
  • Program Committee: IEEE Conference on Tools for AI (Nov. 1990) 
  • Served in a number of EU working groups for AIM, ESPRIT (VLSI, HPCN) 

REVIEWER FOR

  • National Science Foundation (Microelectronics) 
  • IEEE Trans. on Signal Processing 
  • IEEE Trans. on Neural Networks 
  • IEEE Trans. on Computers 
  • IEEE Trans. on Circuits and Systems 

PUBLICATIONS

  • Books
  •  
    1. J. A. Vlontzos “High Performance Parallel Computers”, in preparation 
    2. J.A. Vlontzos “Neural Networks in Signal processing” (Ed.) 
  • Book Chapters 
  • 1.  J. A. Vlontzos and S. Y. Kung, “Digital Neural Network Architecture and Implementation”, in VLSI Implementation of Neural Networks, U. Ramacher editor, Springer Verlag, 1990 
    2.  J.A. Vlontzos and D. Geiger “Active Contours and Dynamic Programming” in “Active Contours” MIT Press 
  • Journal Publications 
  • 1.  Hwang, J. N., Vlontzos, J. A., Kung, S. Y., “ Parallel Architecture and Implementation Considerations for Hidden Markov Models” in IEEE Trans. on ASSP, Dec. 1989
    2.  J. A. Vlontzos and S. Y. Kung “Hidden Markov Models for Computer Vision” in Machine Vision and Applications, Springer Verlag, 1989. 
    3..A. Vlontzos and S.Y. Kung. Hidden Markov models for character recognition. IEEE Trans. Image Processing, 1(4):539--543, 1992. 
    4. Kung S. Y., Vlontzos J. A. and Hwang J. N. “A VLSI Processors for Neural Network Simulation”, in Journal of Neural Network Computing, Auerbach Publishing Co., Vol. 1, No. 4, Spring 1990 
    5. J. A. Vlontzos “Hidden Markov Models for Image Processing” in IEEE Trans. on Signal Processing 
    6.D. Geiger, A. Gupta, L.A. Costa, and J. Vlontzos, "Dynamic programming for detecting, tracking, and matching deformable contours", IEEE Trans. PAMI, vol. PAMI-17, no. 3, pp. 294--302, Mar. 1995. 
  • Conference Publications 
  • 1.  Vlontzos J. A, Kung,S. Y., “A Wavefront Array using Dataflow Processing Elements ”, Proc. Intl’ Conf. on Supercomputers, Springer Verlag, 1987. 
    2.  Vlontzos, J. A., Kung, S. Y., “A Wavefront Array for Signal and Image Processing ”, Tech. Report, USC , 1987 
    3.  Giannakis, G., Manolakos, E. S., Vlontzos, J. A., “Systolic implementation of cumulant and polyspectra based modeling algorithms”, in Proc. IEEE Workshop on Higher Order Spectral Analysis, 1989. 
    4.  Hwang, J. N., Vlontzos J. A., Kung S. Y., “Parallel Architecture and Implementation for Hidden Markov Models” in Proc. SPIE, Visual Comm. and Image Processing III 1988  
    5.  Vlontzos J. A., Kung S. Y., “ A Hierarchical System for Character Recognition with Stochastic Knowledge Representation”, in Proc. of Int’l Conf. on Neural Networks ICNN88  
    6.  Vlontzos J. A., Kung S. Y., “ Hidden Markov Models for Character Recognition” in IEEE ICASSP’89, Glasgow, Scotland, U. K., May 1989 
    7.  H. C. Fu, J. N. Hwang, S. Y. Kung, W. D. Mao and J. A. Vlontzos “A Universal Digital VLSI Design for Neural Networks” in Proc. IEEE Int’l Joint Conf. on Neural Networks, 1989. 
    8.  Vlontzos J. A., Kung S. Y., “ A Hierarchical System for Character recognition” in IEEE ISCAS89, Portland, Oregon, May 1989 
    9.  Vlontzos J. A., Kung S. Y., “A VLSI Array Neural Network Simulator” in International Conference on Neural Network Computing Dusseldorf, FRG, March 1990. 
    10.  Vlontzos J. A and Kung S. Y. “Special Purpose Array Processor Implementation of Neural Networks”, in Proc. IEEE Int’l Conf. on Tools for AI, Wash. DC, Nov. 1990. 
    11.  Vlontzos J. A. “High Speed Implementation of 1D and 2D Morphological Operations”, Int’l Conf. on Application Specific Array Processors, Barcelona, Spain, Sept. 1991. 
    12. Vlontzos J. A., Geiger D. “A MRF Approach to Optical Flow Estimation”, in Proc. IEEE Conf. on Computer Vision and Pattern Recognition 92. 
    13. D. Geiger, J.A. Vlontzos, "Matching Elastic contours", IEEE Conf. on Computer Vision and Pattern Recognition, pp. 602-604, New York, June 1993.
    14. H.C. Karathanasis and J.A. Vlontzos, “VLSI Architectures for Accurate Motion and Disparity Estimation Using Full--Search Block Matching and Edge Preserving Non--Linear Smoothing”, in VLSI Signal Processing VI, Proc. of the 1993 IEEE Workshop on VLSI Signal Processing, L.D.J. Eggermont, P. Dewilde, E. Deprettere, J. V. Meerbergen, Eds, pp. 75-83, IEEE press, 1993. 
    15 H.C. Karathanasis and J.A. Vlontzos, “Fast VLSI Implementations for MRF and ANN Applications”, in Neural Networks for Signal Processing III, Proc. of the 1993 IEEE Workshop on Neural Networks for Signal Processing, C.A. Kamm, G.M. Cuhn, B. Yoon, R. Chellappa and S.Y. Kung, Eds, pp. 460-469, IEEE Press, 1993. 
    16. J.A. Vlontzos, H.C. Karathanasis and I.C. Karathanasis, “Fast MRF Algorithms and Architectures for Image Restoration, Segmentation and Coding”, in Proc. of the 8th IEEE Workshop on Image and Multidimensional Signal Processing, Sept. 1993. 
    17. C.N. Potamianos, J.A. Vlontzos and H.C. Karathanasis, “Services and Uncommitted CAD Environment offered by Intracom's Center of Microelectronics”, presented at the CAVE'94 Workshop, Sesimbra, Portugal, Sept. 1994. 
    18. I.C. Karathanasis, D. Kalivas, J.A. Vlontzos, “An MRF Approach to High Compression Video Coding”, HAMLET Workshop 1995. 
    19. I.C. Karathanasis, D. Kalivas, J.A. Vlontzos, “Disparity Estimation Using Block Matching and Dynamic Programming”, third IEEE International Conference on Electronics, Circuits and Systems (ICECS ’96). 
  • Technical Reports 
  • 1.  J. A. Vlontzos A VLSI Array Neural Network Simulator”, SCR-90-TR273 Nov. 1989 
    2.  J. A. Vlontzos “Biologically Inspired Sensors and their Applications” SCR-90-TR293, May 1990 
    3.  J. A. Vlontzos “Alogorithm Driven Computer Array Design, Methodology and Applications”, SCR-90-TR313, Sep. 1990. 
    4.  J. A. Vlontzos “High Speed Implementation of 1D and 2D Morphological Operations”,SCR-91-TR-336, Spring 1991 
  • Theses 
  • 1.  “Hidden Markov Models for Character Recognition,” Ph. D. Dissertation, University of Southern California, 1989 
    2.  “Correlation Techniques for Zooplankton Classification,” M.Sc Thesis, University of Rhode Island, 1983. 
    3. “TDM FDM Transmultiplexer with Reduced Computational Complexity”, Diploma Thesis, Department of EE, National Technical University of Athens, 1979.