HARALAMBOS (BABIS) C. KARATHANASIS 

BUSINESS ADDRESS

PERSONAL INFORMATION

EDUCATION

Ph.D., Computer Engineering and Informatics, University of Patras, Hellas (1990-1993).
Ph.D. Dissertation: “Algorithms and VLSI Architectures for Digital Image Compression”. Advisor: prof. T.S. Papatheodorou.
Focus: Application Specific VLSI Processors, Digital Image Compression (Hybrid Predictive-Transform Coding, Motion Estimation), MRF-based Statistical Image Processing.

M.Sc., Computer Sciences, Purdue University, U.S.A. (1988-1990). GPA: 5.8/6.
Major: Supercomputing. Advisor: prof. E.N. Houstis.
Minor: Computational Mathematics. Advisor: prof. A. Hadjidimos.
Focus: Parallel Mathematical Software for Solving Partial Differential Equations on Distributed Memory Multiprocessors.

Diploma, Computer Engineering and Informatics, University of Patras, Hellas (1983-1988). GPA: 8.68/10.
Diploma Thesis: “Application of the Kalman Filtering Theory to Image Filtering and Restoration”. Advisor: prof. D.G. Lainiotis.
Focus: Algorithms and Complexity, Scientific Computing, Image Processing, Computer Architecture.

AWARDS

• Purdue University Scholarship (Tuition and Service Award for Research Assistantship), Computer Sciences Department, Purdue University, U.S.A. (1988-1990).
• Hellenic National Scholarships Organisation Award, 1983-1984.
  

PROFESSIONAL EXPERIENCE

12/2005-: Director, Multimedia Systems, INTRALOT, POS Solutions and Multimedia Division, Maroussi, Athens, Hellas.
Responsible for:
 

• Content delivery systems for lottery organisations:
  content and monitor game generation and management, content delivery over IP or DVB networks, content presentation in multiple, geographically dispersed retail shops that may be equipped with TVs, monitors and terminal devices, and, remote presentation control in individual or groups of retail shops or screens.
• Software for self-service lottery terminals and video lottery terminals.

3/2004-11/2005: Section Manager, Multimedia Systems, INTRACOM, Multiservice Networks SBU, Content Delivery Systems Department, Peania, Hellas.
Responsible for embedded systems (software and hardware) for Multimedia and Content Delivery Applications, including Set Top Boxes, DTV/IPTV headend equipment and Conditional Access systems.

Project Manager and Technical Manager, for the development of content delivery systems for a number of international lottery organisations. Those systems are used for creating, delivering, displaying and managing presentation of KENO draws, advertisements, messages and Fixed Odd Betting information (programs, results and odds) in lottery points of sales (retailer shops).

8/2002 - : Adjunct Professor, Athens Information Technology, Peania, Hellas.
Teaching courses and occasionally supervising theses in the area of microprocessors and embedded real-time systems.

11/1999 – 2/2004: Assistant Department Manager, INTRACOM, New Technologies Department, Peania, Hellas.
Responsible for the embedded systems teams performing R&D work in:

• Digital TV Set Top Boxes
• Electronic Program Guides
• Interactive TV applications
• Content Delivery Systems
• Lottery System Solutions
• Fleet Management Systems

Project Manager for the development of Electronic Program Guides and Set Top Box software, for a number of international digital TV operators (DVB satellite and cable).
 

3/1998-10/1999: Group Leader, Embedded Systems, INTRACOM, New Technologies Department, Peania, Hellas.
Established and led the Embedded Systems Group of the New Technologies Department, which:

• focused on the development of a digital satellite TV set-top box (DVB-S/MPEG-2), as well as Interactive TV applications using the OpenTV middleware, and,
• participated in the development of the Digital Broadcast Satellite (DBS) platform of OTE (the Hellenic PTT).

11/1995-2/1998: Microelectronics Projects Co-ordinator, INTRACOM, Development Programmes Department, Peania, Hellas.
Leader of an R&D team (one systems engineer, two VLSI design engineers and four embedded software engineers), that worked in the following projects, partly funded by the EC:
 

• ESPRIT-ΟΜΙ 20287 “ASPIS”: Design - development of a low power System on a Chip (SoC) with embedded ARM7TDMI and custom DSP cores, for the baseband processing (signal processing, protocols and user interface) required in multi-mode DECT/GSM-DCS handsets.
  Role: SoC Architect, Handset prototype System Architect, Technical Manager for the ASPIS project consortium.
• ESPRIT-ESD-LP 25256 “LPGD”: Design – development, using low power techniques, of an integrated circuit for GMSK/GFSK modulation/demodulation required in DECT/GSM-DCS handsets.
  Role: Technical Manager for the LPGD project consortium.
• ESPRIT-OMI 24129 “CODAC”: Hardware-software co-design using the CoWare tools and application of CoWare to the telecommunication system design flow of INTRACOM.
  Role: Project Manager for the INTRACOM team.
   

4/1995-10/1995: Research Associate, INTRACOM, Wireless Communications and Subscriber Systems Department, Peania, Hellas.
Worked on the implementation of the CCITT G.728 speech compression standard, on the Texas Instruments TMS320C50 DSP.
Performed a feasibility study for the implementation of CCITT G.728 in VLSI.
 

4/1994-10/1995: Programmer, Hellenic Army General Staff, Informatics Division, Holargos, Hellas.
Developed a user-interface and a multi-user version (under NOVELL network), for the war-game “IDAHEX”.
 

9/1990-3/1994: VLSI Design Engineer, INTRACOM, R&D Department, Peania, Hellas.
Worked in Application Specific Integrated Circuit (ASIC) design and ASIC design methodologies. Introduced VHDL and Automatic Synthesis tools in INTRACOM’s VLSI design methodology. Designed the first two INTRACOM ASICs that exceeded 15000 gates each (“EDGES” and “SIGMOID” ASICs).

Contributed in a number of research projects partly funded by the EC, in the following areas:
 

• Architectural design of an integrated MPEG-2 decoder, mainly of the Discrete Cosine Transform and Motion Compensation units (project EUREKA-VADIS).Design of a systolic array for motion and disparity estimation, for stereoscopic video compression applications (project RACE-DISTIMA).
• Design of integrated circuits for a statistical image processing system based on Markov Random Field (MRF) models (project ESPRIT-QUICKCHIPS).
• Methodology for hardware - software co-design (project ESPRIT-INSYDE).
   

7/1990-12/1993: Ph.D. Candidate, Department of Computer Engineering and Informatics, University of Patras, Hellas.
Research in Image Compression, MRF-based Statistical Image Processing and VLSI Design.
 

8/1988-7/1990: Research Assistant, Purdue University, Supercomputing Lab, West Lafayette, IN, U.S.A.
Member of the Parallel (//) ELLPACK development team. Research in:
 

• Parallel Algorithms and Mathematical Software on Shared and Distributed Memory Multiprocessors, for Solving: i) Linear Systems with Direct and Iterative Methods, ii) Partial Differential Equations.
• Artificial Neural Networks for 3-D pattern recognition.

5/1988-7/1988: Software Engineer, INTRACOM, R&D Department.
Telecom Software Design.
 

TEACHING EXPERIENCE

Full Courses

• Spring 2005: Co-Instructor (with D. Metafas), “AIT36c – Microprocessors and Embedded Systems” (graduate-level course), Athens Information Technology, 19002 Peania, Attika, Hellas.
• Fall 2004: Co-Instructor (with R. Gandhi, P. Narashimhan, D. Metafas), “AIT1c/CMU13-842 – Fundamentals of Embedded Systems” (graduate-level course), Athens Information Technology / Carnegie Mellon University, 19002 Peania, Attika, Hellas.
• Fall 2003: Co-Instructor (with R. Rajkumar, P. Narashimhan, D. Metafas), “AIT1c/CMU13-849 – Introduction to Embedded Real-Time Systems” (graduate-level course), Athens Information Technology / Carnegie Mellon University, 19002 Peania, Attika, Hellas.
• Fall 2002: Co-Instructor (with R. Rajkumar, P. Narashimhan, D. Metafas), “AIT1c/CMU13-849 – Introduction to Embedded Real-Time Systems” (graduate-level course), Athens Information Technology / Carnegie Mellon University, 19002 Peania, Attika, Hellas.
• Spring 1991: Teaching Assistant (Instructor: prof. T.S. Papatheodorou), “Advanced Scientific Computing” (senior-level course), Department of Computer Engineering and Informatics, University of Patras, Hellas.
• Fall 1990: Teaching Assistant (Instructor: prof. T.S. Papatheodorou), “VLSI Algorithms” (graduate-level course), Department of Computer Engineering and Informatics, University of Patras, Hellas.
• Spring 1990: Instructor, “CS414 - Numerical Methods and Analysis” (senior-level course), Computer Sciences Department, Purdue University, West Lafayette, IN, U.S.A.

Short Courses

• March 2004: Instructor, “Special Topics on Embedded Real-Time Systems”, Athens Information Technology, 19002 Peania, Attika, Hellas.
• April 2003: Co-Instructor (with D. Metafas), “Introduction to Embedded Systems”, part of a Short Course on Advanced Circuits and Systems for Telecom and Multimedia Applications, organized in the framework of the EU/IST-ANTITESYS Project.

STUDENTS

M.Sc.

• M. Makris, “MPEG-2 to IP Gateway”, M.Sc. Thesis, Athens Information Technology, Peania, Athens, Hellas, 2003, (with S. Grigoropoulos).
• P. Panagiotopoulos, “De-jittering of Media Streamed over IP Networks”, Independent Study, Athens Information Technology, Peania, Athens, Hellas, Summer 2003, (with S. Spirou).
• G. Vrahliotis, “Interactive Television Applications”, M.Sc. Thesis in Communication Systems, Department of Electrical & Electronic Engineering, University of Wales, Swansea, U.K., 2001 (with S. Grigoropoulos).
• E. Arslanoglou, “Home-Banking Application Demonstration using OpenAuthor”, Thesis, Post Graduate Training Course in Cable Networks and Communications, University of Lille, France, 2000 (with S. Grigoropoulos).

Undergraduate

• M. Makris, “Development of an Interactive TV Application for Paying Telephone Bills”, Diploma Thesis, Department of Electrical & Computer Engineering, National Technical University of Athens, Hellas, 2001 (with S. Grigoropoulos).

• C. Drosos, “Implementation of MAC layer services for DECT and GSM on the ARM7TDMI processor”, Diploma Thesis, Electrical Engineering Department, University of Patras, Hellas, 1997.

• K. Aretos, “Design and VHDL simulation of a very fast Discrete Cosine Transform Circuit”, Diploma Thesis, Computer Engineering and Informatics Department, University of Patras, Hellas, 1993.

• S. Lazaris, “Design and FPGA implementation of a Vector Rotation Circuit using the Booth Algorithm”, Diploma Thesis, Electrical Engineering Department, University of Patras, Hellas, 1993 (with J.C. Karathanasis).

OTHER PROFESSIONAL ACTIVITIES

1/2003-5/2004: Reviewer, General Secretariat for Research and Technology, Ministry of Development, Hellas.

RESEARCH INTERESTS

• Content Delivery
• Wagering Systems
• Embedded Real-Time Systems
• IPTV, Digital Interactive TV
• VLSI, System On Chip (SoC) Design
  

LANGUAGES

Greek, English.

PUBLICATIONS

I. Theses

[TH1] H.C. Karathanasis, “Algorithms and VLSI Architectures for Digital Image Compression”, Ph.D. Dissertation, Computer Engineering and Informatics Department, University of Patras, Hellas, 1993.
[TH2] H.C. Karathanasis, “Application of the Kalman Filtering Theory to Image Filtering and Restoration”, Diploma Thesis, Computer Engineering and Informatics Department, University of Patras, Hellas, 1988 (in Greek).

II. Journals
[J1] H.C. Karathanasis, C. Dre, D. Metafas, S. Blionas, “Designing a DSP for DECT and GSM/DCS-1800 Baseband Processing”, Real Time Magazine, No. 3, pp. 22-31, July 1996.
[J2] H.C. Karathanasis, “A Low ROM Distributed Arithmetic Implementation of the Forward/Inverse DCT/DST Using Rotations”, IEEE trans. on Consumer Electronics, Vol. 41, No. 2, pp. 263-272, May 1995.
[J3] H.C. Karathanasis, “On Computing the 2-D Discrete Cosine Transform Using Rotations”, Microprocessing and Microprogramming, Vol. 38, No. 1-5, pp. 359-365, Sept. 1993
.
III. Conference Papers
[C1] H.C. Karathanasis, V. Tzovla, I. Misedakis, G. Vrahliotis, M. Makris, V. Kapoulas, C. Bouras, “Delivering Interactive Enhanced Sports Content to Thin-Client DTV STBs”, International Conference on Cross-Media Service Delivery, Santorini, Hellas, 30-31 May 2003.
[C2] S. Tsasakou, C. Dre, H.C. Karathanasis, A. Birbas, “Combined Assessment of an Industrial Current Practice and CoWare’s Methodology for the Co-design / Co-simulation Problem”, MEDEA/ESPRIT Conference on HW/SW Co-Design, Grenoble, France, 16-18 Sept. 1998.
[C3] S. Tsasakou, N. Voros, H.C. Karathanasis, C. Valderrama, S. Arab, M. Birbas, A. Birbas, “A HW-SW Co-Design Methodology For Embedded Telecommunication Systems”, European Multimedia, Microprocessor Systems and Electronic Commerce - EMMSEC ’98, Bordeaux, France, 28-30 Sept. 1998.
[C4] E.N. Frantzeskakis, D. Doumenes, D. Tsimplis, H.C. Karathanasis, A. Theodorou, V. Kassouras, “Digital Implementation of Tamed Frequency Modulation for Medium Rate Radio Transceivers”, International Conference on Telecommunication Networks and Systems Development, “Telecom 96”, Varna, Bulgaria, 2-4 October 1996.
[C5] H.C. Karathanasis, C. Dre, D. Metafas, S. Blionas, “On the Design of a Baseband Processor for DECT and GSM/DCS-1800”, in Embedded Microprocessor Systems, IOS press, pp. 453-462, Proceedings of EMSYS'96, Berlin, September 23-24, 1996.
[C6] D. Metafas, H.C. Karathanasis, S. Blionas, “Industrial Approach in Design Methodologies for Mobile Communications Systems”, Proceedings of the 7th International Workshop on Rapid System Prototyping, Porto Carras, Thessaloniki, Hellas, pp. 122-126, June 19-21, 1996.
[C7] H.C. Karathanasis, E.N. Frantzeskakis, I.C. Karathanasis, A.N. Birbas, “An Efficient Rotation Circuit and its Applications in VLSI Transform Processors'', Proceedings of the 20th Euromicro Conference, Liverpool, England, Sept. 5-8, pp. 499-505, 1994.
[C8] P. Merakos, E. Mariatos, M. Birbas, A. Birbas, E. Frantzeskakis, H.C. Karathanasis, “Efficient Mapping of Cepstrum Algorithms on a Reconfigurable CORDIC System”, Proceedings of the 20th Euromicro Conference, Liverpool, England, Sept. 5-8, pp. 597-602, 1994.
[C9] E. Frantzeskakis, H.C. Karathanasis, “On Computing the 2-D Modulated Lapped Transform in Real-Time”, in VLSI Signal Processing VI, Proc. of the 1993 IEEE Workshop on VLSI Signal Processing, L.D.J. Eggermont, P. Dewilde, E. Deprettere, J. V. Meerbergen, Eds, pp. 361-369, IEEE press, 1993.
[C10] H.C. Karathanasis, J.A. Vlontzos, “VLSI Architectures for Accurate Motion and Disparity Estimation Using Full-Search Block Matching and Edge Preserving Non-Linear Smoothing”, in VLSI Signal Processing VI, Proc. of the 1993 IEEE Workshop on VLSI Signal Processing, L.D.J. Eggermont, P. Dewilde, E. Deprettere, J. V. Meerbergen, Eds, pp. 75-83, IEEE press, 1993.
[C11] H.C. Karathanasis, J.A. Vlontzos, “Fast VLSI Implementations for MRF and ANN Applications”, in Neural Networks for Signal Processing III, Proc. of the 1993 IEEE Workshop on Neural Networks for Signal Processing, C.A. Kamm, G.M. Cuhn, B. Yoon, R. Chellappa and S.Y. Kung, Eds, pp. 460-469, IEEE Press, 1993.
[C12] J.A. Vlontzos, H.C. Karathanasis, I.C. Karathanasis, “Fast MRF Algorithms and Architectures for Image Restoration, Segmentation and Coding”, in Proc. of the 8th IEEE Workshop on Image and Multidimensional Signal Processing, Sept. 1993.
[C13] N.P. Chrisochoides, E.N. Houstis, H.C. Karathanasis, P.N. Papachiou, J.R. Rice, M.K. Samartzis, E.A. Vavalis, K.Y. Wang, S. Weerawarana, “//ELLPACK: A Numerical Simulation Programming Environment for Parallel MIMD machines”, in. Proc. of the 4th International Conference on Supercomputing, June 1990.

IV. Conference Presentations

[PR1] H.C. Karathanasis, ‘Digital Interactive TV in the Convergence Era – Combining Content Distribution and Home Networks’, Electronika 2003, Athens, Hellas, Nov. 15-17, 2003.
[PR2] H.C. Karathanasis, ‘Digital IRDs and Interactive TV Applications’, 7th SIMOS Workshop on Multimedia in Broadcast Networks, Santorini, Hellas, June 28 – 29, 1999.
[PR3] C.N. Potamianos, J.A. Vlontzos, H.C. Karathanasis, “Services and Uncommitted CAD Environment offered by Intracom's Center of Microelectronics”, presented at the CAVE'94 Workshop, Sesimbra, Portugal, Sept. 1994.

V. Invited Talks

[IT1] H.C. Karathanasis, ‘Embedded Systems: Professional Opportunities and Education’, Information Day “The New Role of the Computer Science and Technology”, Univ. of Thessaly, Department of Computer & Communications Engineering, Volos, Hellas, June 7th, 2003.
[IT2] H.C. Karathanasis, ‘New Trends in Digital Interactive TV Technology and Services’, IEE Hellas, Athens, Hellas, Nov., 2001.
[IT3] H.C. Karathanasis, ‘Digital TV and Interactive Services’, Univ. of Thessaly, Department of Computer & Communications Engineering, Volos, Hellas, Nov., 2000.

VI. Technical Reports (selection)

[TR1] C. Drosos, H.C. Karathanasis, C. Dre, D. Karkas, ‘DECT/GSM Data Flow’, Project ESPRIT-20287 (ASPIS) deliverable C/002/a1, Version 2, April 1998.
[TR2] S. Tsasakou, C. Dre, H.C. Karathanasis, “High-level model of MAC-layer processes”, Project ESPRIT-24129 (CODAC) deliverable D4, Sept. 1997.
[TR3] H.C. Karathanasis, C. Dre, V. Bella, “ASPIS Processor System Architecture (Core and Peripherals)”, Project ESPRIT-20287 (ASPIS) deliverable D2.1.R1, July 1997.
[TR4] C. Dre, H.C. Karathanasis, S. Tsasakou, “ASPIS Processor Building Blocks Design Report (memory-mapped)”, Project ESPRIT-20287 (ASPIS) deliverable D3.1.R1, July 1997.
[TR5] H.C. Karathanasis, V. Bella, S. Blionas, D. Dervenis, C. Dre, ‘Market Input Report for Multi-mode Terminal Specifications’, ASPIS project deliverable D6.1.R1, Version 4, June 1996.
[TR6] H.C. Karathanasis, D. Metafas, D. Karkas, “DECT Source Algorithmic Components”, Project ESPRIT-20287 (ASPIS) deliverable D0.1S1, March 1996.
[TR7] I.C. Karathanasis, H.C. Karathanasis, “Netlist, Third Demonstrator ASIC: SIGMOID chip”, project ESPRIT-6043 (QUICKCHIPS) deliverable, June 1994.
[TR8] H.C. Karathanasis, I.C. Karathanasis, “Netlist, Second Demonstrator ASIC: EDGES chip”, project ESPRIT-6043 (QUICKCHIPS) deliverable, July 1993.
[TR9] H.C. Karathanasis, J.A. Vlontzos, “Motion Compensation and Intepolation Units Architecture”, project EUREKA-625 (VADIS) document, Nov. 1992.
[TR10] H.C. Karathanasis, “Frame Buffer Management and Half-Pel Filtering”, project EUREKA-625 (VADIS) document, Sept. 1992.
[TR11] H.C. Karathanasis, E. Marcozzi, S. Ravaglia, V. Rampa, “MPEG-2 CODEC Implementation Proposal, ‘Pel-Split’ Compatible Coding Scheme”, project EUREKA-625 (VADIS) document, Nov. 1991.
[TR12] H.C. Karathanasis, E. Marcozzi, S. Ravaglia, V. Rampa, “MPEG-2 Decoder: Algorithm and Architecture, ‘Pel-Split’ Compatible Coding Scheme”, project EUREKA-625 (VADIS) document, Sept. 1991.
[TR13] H.C. Karathanasis, N. Pronios, “MPEG-2 Decoder Frame Buffer Management”, project EUREKA-625 (VADIS) document, April 1991.
[TR14] C.E. Guerra, E.N. Houstis, H.C. Karathanasis, “Massivelly Parallel Approaches to 3-D Vision”, Computer Technology Institute, P.O. Box 1122, 26110 Patras, Hellas, Technical Report, August 1990.
[TR15] C.E. Guerra, C.E. Houstis, E.N. Houstis, H.C. Karathanasis, S. Kortesis, T.S. Papatheodorou, N.B. Tsantanis, “Massively Parallel Distributed Computing Models for 3-D Vision and Parallel Processing of Scientific Computations”, Computer Technology Institute, P.O. Box 1122, 26110 Patras, Hellas, Technical Report, June 1990.
[TR16] N.P. Chrisochoides, E.N. Houstis, H.C. Karathanasis, P.N. Papachiou, J.R. Rice, M.K. Samartzis, E.A. Vavalis, K.Y. Wang, “Parallel (//) ELLPACK PDE Solving System”, Computer Sciences Dept., Purdue University, Technical Report CSD-TR-912, CAPO Report CER-89-20, October 1989.